Chipsets of the modern computer systems become a broadly used device for controlling data read/write operations from/to IDE devices because IDE standards offer many useful advantages. Those advantages, such as low cost, excellent compatibility, and easy for set up, bring on the IDE bus to be one of the most popular interfaces.
PIO and direct memory access (DMA) are two commonly used approaches (modes) for data transmission, and every one aforementioned can be selected for transferring data with the IDE devices via the IDE interface. Both of the PIO and DMA modes can establish paths for delivering data via the IDE interface between the host systems and the IDE devices.
In the PIO modes, the processing unit of the host system generates input/output (I/O) commands for activating relative read or write operations between the IDE devices and the memory or between the IDE devices and other interfaces under controlled by the chipset of the host system.
The PIO input/output (IO) modes consist of:
IO mode 0: The maximum rate for data transmission is 3.3 MB/sec
IO mode 1: The maximum rate for data transmission is 5.2 MB/sec
IO mode 2: The maximum rate for data transmission is 8.3 MB/sec
IO mode 3: The maximum rate for data transmission is 11.1 MB/sec
IO mode 4: The maximum rate for data transmission is 16.6 MB/sec
The higher number of the I/O mode indicates the better efficiency of the data transmission under the IDE interface.
The read and write operations under the PIO modes are briefly illustrated below. In the reading steps of the PIO modes, the processing unit issues read commands to the chipset, while the chipset accesses data from the IDE device and then puts the accessed data into memory for the use of the processing unit. Under writing steps of the PIO modes, the processing unit issues write commands to drive the chipset to retrieve data from the memory, while the retrieved data is then put into the indicated IDE device. Conventionally, associated interrupts are issued for activating data transmission for read or write operations under PIO modes.
FIG. 1 is a diagram illustrative of the data transmission operations in the conventional IDE interface system. In this firmware configuration under PIO mode, operating system 10 transfers data in responsive to a write command via the PCI interface 20 or other interfaces 30 (such as IEEE 1394, USB interface) into the IDE controller 40 under the PIO modes. A buffer 42 in the IDE controller 40 is used for temporarily storing the transferred data while—the data stored in the buffer 42 is finally delivered to the IDE device 50 via the IDE interface 60. Additionally, when a read command is issued, the data indicated by the read command in the IDE device 50 is transferred into the buffer 42 via IDE interface 60 and the firmware control interface 44. The transferred data is then delivered out of the IDE controller 40 via the PCI interface 20 or other interfaces 30 for the use of the processing unit. As noted, firmware control interface 44 handles data transmissions activated by interrupts between the IDE device 50 and the PCI interface 20 or the other interface 30. However, to activate interrupts for starting read or write operations significantly burdens firmware loading and affects data transmission performance.
Associated firmware will be driven for handling data transmission under the PIO modes as mentioned above. Basically, the transmission cycle time is about 120 ns (nanoseconds) under IO mode 4 of the PIO modes. Therefore one read/write (IOR/IOW) operation should be completed within 120 ns in order to achieve the purpose of most efficiently transferring data in and out of the IDE device 50 via the IDE interface 60. Unfortunately, the above requirement is seldom accomplished because the conventional firmware configuration manipulating data transmission is usually limited by the performance of the processing unit. This implies that the required data may not be delivered following the fastest transmission speed under the IO mode 4.